`timescale 1ns / 1ps
//Name: Robert Smith
//PID: A08609119
//Name: Shreenidhi Chowkwale
//PID: A09089080
//
// CSE141L Lab 2, Part 1: Fetch Datapath
// University of California, San Diego
//
// Written by Donghwan Jeon, 4/10/2007
// Updated by Sat Garcia, 4/8/2008
// Updated by MBT, 4/4/2011

// 2 input Mux
//
// parameters:
// 	WIDTH: data width for inputs and output
//
module mux#(parameter WIDTH=10)
(
	input		sel_i,
	input		[WIDTH-1:0] d0_i,
	input		[WIDTH-1:0] d1_i,
	output	[WIDTH-1:0] d_o
);

reg [WIDTH-1:0] d_next;

// if sel_i == 0, d_o = d0_i, otherwise, d_o = d1_i
always_comb
	begin
		case (sel_i)
			1'd0 : d_next = d0_i;
			1'd1 : d_next = d1_i;
			default : d_next = {WIDTH-1{1'bx}};
		endcase
	end
	
assign d_o = d_next;
endmodule
